1. Field
Example embodiments relate to a storage device, for example, to a device and a method for operating and manufacturing a non-volatile and electrically erasable semiconductor memory device, for example, a flash memory.
2. Description of the Related Art
Non-volatile memory retains information stored in its memory cells even when no power is supplied. Examples include mask ROM, EPROM, and EEPROM.
Non-volatile memory is widely used in various kind of electronic products, for example, personal computers, personal digital assistants (PDAs), cellular phones, digital still cameras, digital video cameras, video game players, memory cards, and other electronic devices.
Memory cards types may include multimedia cards (MMC), secure digital (SD) cards, compact flash cards, memory sticks, smart media cards, and extreme digital (xD) picture cards.
Among non-volatile memory devices, a flash memory is widely used. Flash memory may be divided into a Not-OR (NOR) type and a Not-AND (NAND) type based on a connection structure of cells and bit lines. Because a read speed is faster and a write operation is slower, a NOR-type flash memory may be used as a code memory. Because a write speed is faster and a price per unit area is lower, a NAND-type flash memory may be used as a mass storage device.
NOR-type flash memory may be used in BIOS/networking in a PC, a router, or a hub or in a telecommunications switcher. NOR-type flash memory may also be used to store code or data for cellular phones, personal digital assistants (PDAs), POS, or PCA.
NAND-type flash memory may be used in memory cards for mobile computers, digital cameras, both still and moving, near-CD quality voice and audio recorders, rugged and reliable storage, for example, solid-state disks.
The programming method for NOR-type flash memory is hot carrier injection and the programming method for NAND-type flash memory is Fowler-Nordheim (FN) tunneling.
Advances in consumer electronics cause demand for higher density memory devices. Efforts to manufacture devices meeting this demand often involve scaling down the sizes of gate structures and reducing or minimizing the space between adjacent gate structures.
With the reduction in channel length of transistors, the influence of a source and drain upon an electric field or potential in the channel region may increase. This is referred to as the ‘short channel effect’.
Other related problems include trap-assisted leakage current. As shown in FIG. 37, in a conventional charge trap memory device 10, including a substrate 12, a tunnel insulating pattern 14, a charge storage pattern 16, a blocking insulating pattern 18, and a conductive pattern 20, electrons e− may leak from the charge storage pattern 16 through blocking insulating pattern 18 to the conductive pattern 20, for example, as a result of one or more defects D in the blocking insulating layer.
Conventional art publications have studied the characteristics of non-overlapped MOSFETs, and reported that performance degradation was suppressed by using a short non-overlap distance, for example, less than 10 nm. These results indicate that a non-overlapped structure is practically applicable.
Referring now to a conventional device from U.S. patent application Ser. No. 11/643,022, filed on Nov. 20, 2006, the entire contents of which are hereby incorporated by reference in their entirety, shown in FIG. 38, a memory may include a substrate 10, a channel region 40cC, a fringing field 90, an inversion layer 410, and an inversion layer at a source/drain region 430. As shown, a pass voltage of 5 V may be applied to memory transistors MTn−1 and MTn+1, and a select voltage Vsel may be applied to memory transistors MTn. The fringing field 90 from the cell gate potential may cause source/drain inversion, which enables the channel region to conduct a charge.
Referring now to a conventional device from U.S. Pat. No. 7,081,651, shown in FIG. 39, a gate conductive pattern may be patterned to form a plurality of wordlines 140 crossing the first active regions 103 in the cell array region “a”, and to form a gate electrode 240 at least on the second active region 203 in the peripheral circuit region “b”.
The third insulating pattern 106 exposed between the plurality of wordlines 140 may be overetched or attacked by plasma while etching the gate conductive pattern. Therefore, a defect site may be created in the third insulating pattern 106 around an edge of a wordline 140. Subsequently, a trap-to-trap tunneling may occur through the defect site. Charges stored in a later-formed charge storage pattern may then be discharged to a gate electrode, having an undesirable influence on device operation.
Referring now to a conventional device from U.S. Pat. No. 6,674,122, shown in FIG. 40, a semiconductor integrated circuit device may include nonvolatile memory cells, each of which includes one memory transistor TMC and two switch transistors TSW, wherein the memory transistor TMC includes a memory gate electrode 7 connected to a word line 5. The switch transistors TSW may each include a switch gate electrode 6-1 and 6-2, an inversion layer 20-1 and 20-2 which is formed below the switch gate electrode 6-1 and 6-2 by applying a voltage to the switch gate electrode 6-1 and 6-2, the inversion layer 20-1 and 20-2 functioning as a source or a drain of the memory transistor TMC.